We are coming-up with our 3rd center in India @ Noida soon..

Certificate Program in VLSI Logic Design, Layout Design Engineering
TIIT in collaboration with the University Of California at Santa Cruz Extension in the Silicon Valley and Cadence Design Systems offers a certificate in program in VLSI design engineering. Students who complete the required courses with minimum grade  more...

We are coming-up with our 3rd center in India @ Noida soon..

Certificate Program in VLSI Logic Design, Layout Design Engineering
TIIT in collaboration with the University Of California at Santa Cruz Extension in the Silicon Valley and Cadence Design Systems offers a certificate in program in VLSI design engineering. Students who complete the required courses with minimum grade point average (GPA) will be awarded a certificate in VLSI design engineering (Physical Design or Logic Design) from the University Of California Santa Cruz extension in Silicon Valley.

Course: Updated Exclusive courses for Layout Design & Logic Design Engineering (Back-end & Front-end)
Duration: Will be tentatively for 20 weeks.
Classes Time: Classes will be in the evening And weekends for Tool related classes.
Fees: The fee is You can make it in 3 Installment.
Placements: We will not give the Guarantee of job; we will provide Placement assistance with MNC Semiconductor Industry, 96% of the people got the job so far???

Start Date: July 10th, 2007 In Bangalore, may 1st week in Hyderabad.
Prerequisites:

BE/BTech/ME/MTech/MSc in either computer science or Electrical/Electronics

Registrations: Open Online @ (www.tiit.in ) for Bangalore.

Course contents:
You can see: http://tiit.in/courses.html.
?? VLSI and ASIC Design, Introduction
?? Introduction to IC manufacturing
?? General Instruction
?? VLSI Engineering Fundamentals
?? DFT Concepts for ASIC Design, Practical Application
?? Class room sessions
Logic Synthesis
?? Advance ASIC Physical Design
?? Practical Sessions
?? Static Timing Analysis System Integrity in SOC Design
?? Self-Learning
?? Student Seminars

The following tools from Cadence will be used for the training:
?? SOC Encounter X, Encounter ATPG, Incisive Unified Simulator, RTL
?? Compiler XL with BG and CTE, Virtuoso XL Layout Editor, Assura DRC/LVS,
?? Assura RC, Virtuoso Schematic Entry.
?? Celtic Cross Talk Analysis for Signal Integrity Analysis.
?? VoltageStorm IR drop analysis Tools for Signal Integrity Analysis
?? NanoRoute Global/Detail Router.
?? verilog simulation- NCSim.
?? Synthesis - RTL Compiler.
?? System Verilog - NCSIM.DFT - RTL Compiler.
?? STA- CTE Engine.

Instructors: : Instructors are coming from the Industry Like Cadence, PMC sierra,Intel & Ttm.
Screening Test: Screening test comprises of basic digital electronics & Aptitude. Multiple-choice question.

Make sure: Since we will In-take only 20 Students per batch, we are getting advance booking for Batches, make sure you will get the seat.

For more info: :
www.tiit.in
www.time2mkt.com/training.html
www.cadence.co.in/support/university/ww_usp.aspx
www.ucsc-extension.edu/ucsc/onsitetraining/vlsi.jsp

Shashi.Deshpande
TIIT Pvt,Ltd.
#18,1st Floor,Palavalli Plaza.
100 feet ring road.2nd stage,
BTM Layout. Bangalore-76
Tel: +91-08-26789654.
Cell: 9845261676.